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Power-Aware real-time scheduling

Units : Parallel Architectures for Real-Time Systems | ULB709

Description :

Energy consumption and battery lifetime are nowadays major constraints in the design of mobile embedded systems. Amongst all
hardware and software techniques aimed at reducing energy consumption, supply voltage reduction, and hence reduction of CPU speed, is
particularly effective. This is because CPU requires a large amount of energy (e.g., 30W at maximal frequency for an Intel P4
Mobile 1.8GHz[1]) and the energy consumption of the processor is usually at least quadratic in the speed of the processor (see [1] for
more details). The aim is thus to minimize the processor frequency as much as possible while satisfying the performance
constraints of the system.       Many power-constrained embedded systems are built upon multiprocessor platforms because of
high-computational requirements and because multiprocessing often significantly simplifies the design. As pointed out in [2] and [3], another
advantage is that multiprocessor systems are theoritically more energy efficient than equally powerful uniprocessor platforms because
raising the frequency of a single processor results in a multiplicative increase of the consumption while adding processors leads
to an additive increase.      We address the problem of determining one or several processor speeds which involve significant
power savings while system is running. The determined speeds must satisfy all the temporal constraints of the system. In the second
part of our research, we investigate the various models of battery and include their behavior into the scheduling algorithms in
order to take into account a more realist supply voltage delivery.

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